With the rapid development of integrated circuit fabrication processes, cells in modern integrated circuits are fabricated in a more compact manner and have smaller pitches than cells in conventional integrated circuits. For example, pitch requirements for integrated circuit fabrication processes have evolved from micron level to nanometer level. Accordingly, lithography has to be precisely performed in order for layout patterns to be accurately exposed via masks before being mapped to semiconductor wafers.
Photoresist materials are used with patterning and etching techniques to form structures such as integrated circuit layouts. In particular, integrated circuit layout geometries have dramatically decreased in size. As the integrated circuit layouts decrease in size, so do the layouts of the photoresist material used to pattern the features into the integrated circuit layouts. Photoresist material may be deposited, exposed, and then developed to create the photoresist pattern. When immersion development is utilized, the developing solution may be rinsed from the integrated circuit layout with deionized water. With smaller feature sizes, the adhesion force of the photoresist material to an anti-reflective coating (ARC) or even an adhesion promoting layer deposited on the ARC layer may approach the point where the capillary force of the drying water exceeds the adhesion force. When the capillary force exceeds the adhesion force, the pattern may collapse, especially in areas including dense line patterns and sparse line patterns adjacent to each other. If the pattern collapses, the integrated circuit layout becomes defective because effective etching of features into the integrated circuit layout cannot be performed.
Therefore, there is a need for a model of defining a photoresist pattern collapse rule, as well as for a photomask layout, a semiconductor substrate and a method for improving photoresist pattern collapse.